Different width of signals

[Kosyas41]

Hi,
Could you pls help me,I faced with next problem, I have to signals,one signal is 31 bits width,and the other is 16 bits,how to connect it together?

tx_sample_i      : signed(15 downto 0)
s_out : std_logic_vector(31 downto 0)
s_out => tx_sample_i

which conversion should I do?

 

[ads-ee]

Maybe this will help https://www.bitweenie.com/listings/vhdl-type-conversion/
along with using resize first to make the bit widths match.

I think it's something like "std_logic_vector(resize(tx_sample_i, s_out'length))".

 

[FvM]

You are copying a signed entity to std_logic_vector which needs explanation. What do you want to achieve? Sign extend the signed number to 32 bit? Left adjust the 16 bit number? Ignore the signed nature and fill the result with zero bits?

You should code the logic operation that is required by your specific application. We can't know what it is.

 

[Kosyas41]

I already checked that link/and I know how to convert.My fft engine produce two outputs,each 32 bits width std_logic_vector,after this I want to connect this output whit thransiver input.which has only 16 signed width signal.