Difference between the design variable and component parameters in cadence virtuoso

[noor84]

Hi all,

Could you please explain what is the difference between using the design variable and component parameters in cadence virtuoso?
Also the parametric analysis in ADEL?

I need to measure the ID Vs VDS and The ID vs VGS of the transistor.

Regards.

 

[dick_freebird]

The instance parameter may be an ADE (Spectre) variable,
or a number. If a form-value is one that gets into the netlist
line, and it is not recognized as a plain number (int or FP)
then off to the "variables bin" it goes.

I have only ever used variables as indices of Parametric
Analysis. Evidentyly you can instead loop an instance's
device attributes (or subset thereof) ala SPICE .alter.

While it's possible, modern PDK construction may make
it difficult (finding the proper name as Spectre / ADE sees
it, likely not what you call it inm the schematic; "buried"
subcircuit code and netlisting may need some interpreting
or use a "test" plot command to get at the root name).
You may have to explore how / whether you can get at a
specific instance's sub-element(s), in what ways, for what
parameters.

But if your PDK is set up unpleasantly you may not be able
to get at the lower level elements. Like in a RF CMOS FET
model, your actual transistor is likely to be bedded inside
parasitic elements and named differently than what you
see on the schematic, and that chain of netlisting makes
a Spectre block.block.block.deviceName which you'll have
to get, but may not be able to get, through the GUI without
some netlist digging. Do that in a foreground simulation to
get the "magic names" and then you can set up PA (may as
well get the Calculator expressions sorted at the same time
as well).

 

[noor84]

The instance parameter may be an ADE (Spectre) variable,
or a number. If a form-value is one that gets into the netlist
line, and it is not recognized as a plain number (int or FP)
then off to the "variables bin" it goes.

I have only ever used variables as indices of Parametric
Analysis. Evidentyly you can instead loop an instance's
device attributes (or subset thereof) ala SPICE .alter.

While it's possible, modern PDK construction may make
it difficult (finding the proper name as Spectre / ADE sees
it, likely not what you call it inm the schematic; "buried"
subcircuit code and netlisting may need some interpreting
or use a "test" plot command to get at the root name).
You may have to explore how / whether you can get at a
specific instance's sub-element(s), in what ways, for what
parameters.

But if your PDK is set up unpleasantly you may not be able
to get at the lower level elements. Like in a RF CMOS FET
model, your actual transistor is likely to be bedded inside
parasitic elements and named differently than what you
see on the schematic, and that chain of netlisting makes
a Spectre block.block.block.deviceName which you'll have
to get, but may not be able to get, through the GUI without
some netlist digging. Do that in a foreground simulation to
get the "magic names" and then you can set up PA (may as
well get the Calculator expressions sorted at the same time
as well).

Thank you for your reply,

Sorry, I did not understand what you mean exactly ( I am beginner to cadence),
can you explain what is the steps and the difference for '
Could you please explain what is the difference between using the design variable and component parameters in cadence virtuoso? Also the parametric analysis in ADEL?
I need to measure the ID Vs VDS and The ID vs VGS of the transistor.?

Regards.

 

[noor84]

Hi all,

I am training to make simulation for ID with VDS only,
I can get the curve of ID with VDS by using design variable and I can get the same result if I use the Component parameter.

So, my question is what is the differences between them (design variable and Component parameter) as long as I get the same result?



if I want to find the curve of ID, VGS, VDS then I have to use the parametric analysis.

Please, I need answer.