Difference Between QOR in Optimization Log and report_qor Command (ICC)

[Antonius Perdana Renardy]

Hi,

I was doing psynopt command using ICC and when the last stage of optimization had completed the log showed something like this:

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Placement Optimization Complete
  -------------------------------
 
Information: T8    CPU:  13329 s ( 3.70 hr) ELAPSE:   3140 s ( 0.87 hr) MEM-PEAK:  5264 Mb   Mon Jan  4 19:31:26 2016  (PSYN-508)
Information: T9    CPU:  13336 s ( 3.70 hr) ELAPSE:   3148 s ( 0.87 hr) MEM-PEAK:  5264 Mb   Mon Jan  4 19:31:34 2016  (PSYN-508)
 
  Scenario: setup_slow   WNS: 2.35  TNS: 2.36  Number of Violating Paths: 4
  Scenario: hold_fast   WNS: 0.00  TNS: 0.00  Number of Violating Paths: 0
  Design  WNS: 2.35  TNS: 2.36  Number of Violating Paths: 4
 
 Nets with DRC Violations: 4
  Total moveable cell area: 208221.0
  Total fixed cell area: 526450.9
  Total physical cell area: 734671.8
  Core area: (27000 272300 1289250 1158800)
 
 
 
  Scenario: setup_slow  (Hold)  WNS: 0.00  TNS: 0.00  Number of Violating Paths: 0
  Scenario: hold_fast  (Hold)  WNS: 10.25  TNS: 20.38  Number of Violating Paths: 2
  Design (Hold)  WNS: 10.25  TNS: 20.38  Number of Violating Paths: 2

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Then I checked the QOR using report_qor command and the last few lines of the report are listed below:

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--------------------------------------------------------------------
 
  Scenario: setup_slow   WNS: 2.25  TNS: 4.19  Number of Violating Paths: 107
  Scenario: hold_fast   WNS: 0.00  TNS: 0.00  Number of Violating Paths: 0
  Design  WNS: 2.25  TNS: 4.19  Number of Violating Paths: 107
 
 
  Scenario: setup_slow  (Hold)  WNS: 0.00  TNS: 0.00  Number of Violating Paths: 0
  Scenario: hold_fast  (Hold)  WNS: 10.26  TNS: 20.40  Number of Violating Paths: 2
  Design (Hold)  WNS: 10.26  TNS: 20.40  Number of Violating Paths: 2
 
  --------------------------------------------------------------------

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Number of violating paths for setup timing on the log is different compared to the report_qor command. I previously never encountered something like this; usually the number always the same. Can anybody explain to me why this happened?

Thanks a lot!

Regards,
Antonius

 

[nav_vlsi]

analyze cell displacement during legalization.

This could happen , when during placement optimization, EDA tool can meet timing by sizing / adding cells. however during legalization of those cells, EDA tool may not find a nearest legal location to place those cells. This may be due to local cell density /pin density / local congestion. hence these newly sized / added cells may be thrown out by longer distance from the expected location. This will contribute to extra delay & there by degrading setup time.