difference between buffer and signal and register andbus in

[ahmadagha23]

difference between buffer and register

Hi dear friends
what is difference between buffer and signal and register and bus in vhdl?
thanks

 

[delay]

Re: difference between buffer and signal and register andbus

Buffer is a port type, signal is the physical medium for connectivity, register is syncrhonous logic device and bus is not a VHDL specific reserve word, it could mean a vector. A comparison of these will be simply obscure as these are very much uncorrelated.

 

[ashishjindal76]

hi

think logically, buffer is nothing but an amplifier or repeater providing u a unit delay and improves the fanout., register is 1 bit storage element and is a building block for memories, lut etc, etc.. signal is an interconnect device just like a wire which neither stores any data, nor it provides any delay and at the output, output changes as soon as the input changes which means that it is non triggered device and bus is a bunch of wires.

ashish