dff in vhdl without using a process?

[rastor]

Hello,
I was wondering if it is possible to implement a D flip flop in vhdl without using
process(x)?

I know how to do it using process.

Thank you.

 

[jducluzeau]

No, it is not possible.
process are used for sequential operation.
Outside process this is for combinatorial logic.
DFF is basic element of sequential module.

Regards

 

[rastor]

so we can't use behavioral model to implement dff?
thanks

 

[hareshcooleng]

we can't do without process.

 

[TrickyDicky]

Yes you can. This models a flip flop:

a <= b when rising_edge(clk);

here is a shift register demo written without any processes. Try simulating it:

library ieee;
use ieee.std_logic_1164.all;

entity play_tb is	 
end entity;

architecture rtl of play_TB is  
  signal clk : std_logic := '0';
  
  signal a : std_logic := '1';
  signal b : std_logic_vector(7 downto 0) := x"00"; 
  
begin
  
  clk <= not clk after 10 ns;
  
  b <= ( b(6 downto 0) & a ) when rising_edge(clk);
end rtl;

 

[permute]

vendors usually have a primitive as well. eg, FD, FDRSE, FDCPE, for xilinx. These had a use in getting initial register values with synthesis tools that didn't infer initial values. a couple years ago this was an issue with synplify.

 

[std_match]

Yes you can. This models a flip flop:

a <= b when rising_edge(clk);

Is this guaranteed to work if you synthesize it? It seems to me that the function depends on extremely short pulses that could be a problem in a "real" circuit.

Edit:
If the compiler recognizes this as a D-type flip-flop I understand, but I think it can be implemented with only gates, and then there could be a problem.

 

[TrickyDicky]

This line of code does synthesise properly.
It's nothing to do with pulses, its more about whether the code matches specific templates. For quartus, it sees a register template and places a register. It doesnt measure the length of any "pulse"

PS. This line is also synthesisable, and puts a reset on the register:

b <= '0' when reset = '1' else a when rising_edge(clk);

Single lines on their own are really just processes without the extra words.

 

[std_match]

This is interesting. Until now, I believed that code outside of processes only could result in combinatorial logic.

What about the "sensitivity list" for a one-line process?
For a dff in a normal process, the "data in" is not in the sensitivity list.
For a "one-line" dff process, will a simulator process it when there is a change in any input signal? In that case, the "one-liner" could be less efficient for simulation.

 

[TrickyDicky]

any line outside a process is essentially a process sensitive to all signals on the right hand side.
As you point out, normally you wouldnt put the "d" input into the sensitivity list, but it wont actually hurt anything other than simulation performance as it will evaluate the process whenever D changes as well as clk and reset. But the sesitivity list is ignored for synthesis and logic is generated from the actual code (using known templates) rather than sensitivity lists. This is why you can get simulation/synthesis missmatch for the same code.

For best results though, it would be best to stick to standard practice (all registers created inside a process). There is no garantee that any two synthesisors give the same results for the same "non standard" code.