akeedthe
Junior Member level 1
Hi,
Im doing this project for my FYP and selected this.
Develop a IP Core for Memory Generator [Xilinx]
To use VHDL and develop an IP that will be able to generate different types of memories such as ROM, single, simple dual and dual-port random access memories and SRL 16-based memories. Also these memories will support a range of data depth from 16 -65,536 words and data width ranging from 1- 1K bits. The newly developed IP has to be benchmarked with the Xilinx IPs for their performance with respect to delay and other significant parameters.
From what I understand, im supposed to make an IP Core like the one done by Xilinx and test against it.
Any ideas as to how I can proceed and read up on this?
Everywhere I type IP Core and google I get "how to implement it" not how to make one.
Any advice would be highly appreciated.
Thnx in advance. :-D
Im doing this project for my FYP and selected this.
Develop a IP Core for Memory Generator [Xilinx]
To use VHDL and develop an IP that will be able to generate different types of memories such as ROM, single, simple dual and dual-port random access memories and SRL 16-based memories. Also these memories will support a range of data depth from 16 -65,536 words and data width ranging from 1- 1K bits. The newly developed IP has to be benchmarked with the Xilinx IPs for their performance with respect to delay and other significant parameters.
From what I understand, im supposed to make an IP Core like the one done by Xilinx and test against it.
Any ideas as to how I can proceed and read up on this?
Everywhere I type IP Core and google I get "how to implement it" not how to make one.
Any advice would be highly appreciated.
Thnx in advance. :-D