Design RAM using verilog with port given only

[sukyen]

Can anyone help me to solve this?
Design RAM using "module RAM (ramaddr, ramin, cs, rwbar, opr, ramout);"
with ramaddr, ramin, cs, rwbar, opr as input and ramout as output.

I am new to verilog design and I am wondering why clk isn't included in the port list.
Aren't ramaddr and ramin the same?
What is opr stated in the port list?
I have found a lot of verilog example but still can't figure it out.

 

[zel]

hm.. this is quite new for me too..
what i know from the names, ramaddr is address. ramin is a data. cs is chipselect. rwbar is read/write bar. opr is operation and ramout is data out..