Design Procedure for LDO topology

[massive]

Hi to All,

I would like to ask if someone could give me some info ( paper, or other design document) about the LDO topology that is attached below.

I have not seen it often in papers or LDO design books, etc.

This topology is simple but effective for LDO desgn, to my opinion.

The schematic that is attaced below is simplified and some transistors are not shown
( like cascodes, etc).

Here it is:

Thanks.

 

[massive]

Please guys,
I need this info about the schematic! It is part of important project that I am doing
Thanks in advance!

Best Regards

 

[haff99]

What exactly do you need? It is about as simple as LDO's come. This LDO seems suitable for low output currents. THere are better LDO's for higher current. compensation is easy as the only real spot to compensate is on the output. Gain is simple. It is basically gm of the diff pair, virtually no gain from the second stage due to the diode connected device, times the ratio of the output mirror times the output impedance. You are going to have a systematic offset due the voltage on the drain of the second stage NMOS device since it will be different the the voltage on the NMOS mirror device. That is going to get reflected back to your input since the gain in your first stage is not too high.

 

[massive]

Thanks haff99 for your reply.
What numbers do you mean by saying "low" current and "high" current?
I am looking in the range of 0 to 5 mA.
Could you suggest me better architectures for these currents than this one?

I was looking for a design procedure which explains the compensation if the circuit.
It is not as simple as it looks - the internal poles ( output of diff. pair and P mirror ) will also play role if the ouput pole is not so dominant.

Thanks.

Best Regards,

 

[arghpok]

I don't like the topology at all. the 2nd stage of ur error amplifier is not helping you at all. U need a buffer to increase the error amplifier's output pole frequency and keep the system stable enough at low loads. Since u r using an external cap (i guess) for ur compensation, u may need to increase overall gain to improve performance parameters as line and load regulation (u can do this by simply cascoding 2nd stage). Current capabilities are determined by two main things: 1st, the pass transistor aspect ratio and the operation region u want it to be (typically saturation, although there's a lot of works now with the M pass in linear region as well). 2nd, the control voltage dynamic range, in which i dont see any evident problem. Finally, use for ur transient simulations current sources instead of resistors as the load.

If this is really important to you, you should change error amplifier topology, look around !

 

[sohpie2007]

Try to get a working LDO deisgn from:

**broken link removed**

 

[massive]

Hi sohpie2007,
Very interesting site. I have checked it.
Thanks.

Regards,

 

[quaternion]

Sorry
But ,can anyone tell me how to get designs of that site.

I have seen many here recommend it but I couldn't get any design from there.

 

[jonneylu]

the attahment is a simple ldo topology whic use two stage amplifier.