andrew_ww
Newbie level 2
Hi!
I would like to ask about optimized DFT in practice. In nuthsell, how much time it is supposed to consume to test a new ASIC ? (After it is manufactured, and shipped from the fab.)
If i want less time to test, i should build in more complex self-tests, use more silicon. With zero amount of silicon, still i can test the device by all of its functionality. That just takes more time (much more in this case, it will be a highly integrated logical device with memory and many state machines inside). How should i balance it? For example, i can guess, that a new device may demand 10 milliseconds in the tester, it is okay. What about 1 second? 5 seconds? 10? 200? Where i should think, that time is too much already?
I would like to ask about optimized DFT in practice. In nuthsell, how much time it is supposed to consume to test a new ASIC ? (After it is manufactured, and shipped from the fab.)
If i want less time to test, i should build in more complex self-tests, use more silicon. With zero amount of silicon, still i can test the device by all of its functionality. That just takes more time (much more in this case, it will be a highly integrated logical device with memory and many state machines inside). How should i balance it? For example, i can guess, that a new device may demand 10 milliseconds in the tester, it is okay. What about 1 second? 5 seconds? 10? 200? Where i should think, that time is too much already?