Design Compiler black box and parameter

[blindscience]

I have a parameterized Verilog module foo that I would like to black box during DC synthesis and be able to plug in a simulation-only module later on. Essentially, whenever I've instantiated foo in my design, I would like DC to pass these instantiations (with parameters) through to the mapped Verilog.

I have read multiple techniques for black boxing logic in DC, including a) defining a port-only version of the module in Verilog and b) using
"set_app_var hdlin_sv_interface_only_modules {modulename}" to remove the internals of the module when the definition is pulled in. I have used both of these techniques with the same undesired result.

Specifically, I am running into two problems:
1) After compilation, the generated mapped.v file includes module definitions for instantiations of foo, such as below. This would indicate that DC is not correctly considering foo as a black box:

module fooInstanceParamValue1ParamValue2ParamValue3(
   input porta;
   input portb;
   output portc;
)
endmodule

2) As a related issue, I can't just delete the empty module definitions and plug in my simulation model because, as show above, the parameters to the module have been removed and everything has been elaborated into a specific instance with a custom name.

What am I doing wrong?

Thanks!

 

[blindscience]

I have found a partial solution to my problem. It looks like the
"set_app_var hdlin_sv_blackbox_modules {moduleNames}" command marks a module such that DC no longer includes an empty module definition (problem #1 above).

However, DC still removes the parameters (problem #2 above), now instantiating a bare module as below. In some sense, this is even worse than above since the parameter values are totally gone - I can't write a script to convert the custom instance names back into parameters:

foo fooInstance 
(.portA(wireA[wireWidthA:0]), 
.portB(wireB[wireWidthB:0])
);

--- Updated Aug 24, 2021 ---

I should mention, according to the 2019.09 documentation for DC, the hdlin_sv_blackbox_modules method (which mostly works as expected) is apparently legacy syntax. The preferred method is using the hdlin_sv_interface_only_modules method (which, as far as I can tell, does not work at all).