design and implemenation of viterbi decoder

[setareh_mehr85]

how to design viterbi decoder

hello
I'm doing my final year project design and implementation of virebi deocder, can any one can help me with a source code , I'm using VHDL

 

[RBB]

So you want somebody to do your senior design project for you? Good luck finding somebody that nice.

 

[setareh_mehr85]

No I didnt ask to do design for me I;m half way with my design and done the convo encoder and I aldo did the matlab , I need the codes to compare with my codes because I'm stuck in somewhere, by the way if you cant help don't reply....

 

[RBB]

You can use Matlab to compare the decoder outputs as well. Look into the viterbi function in Matlab.

 

[cmangaraju]

i can help u , could u brief where did u stuck in branch metric unit or path mertic or survivor memory unit.

 

[setareh_mehr85]

i'm using hard decision, my problem is in coding part how to write the code to compare my recievede code with state output and calculate the ham distance , for now I need to solve how to write the code to calculate the hamming distance this the code i write to start up for branchmetric
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

entity branchmetric IS

generic (

Bit_Width : integer := 3;
BM_Width : integer := 4);

port (
input0 : IN std_logic_vector (Bit_Width - 1 downto 0);
input1 : IN std_logic_vector (Bit_Width - 1 downto 0);
bm00 : OUT std_logic_vector(BM_Width - 1 DOWNTO 0);
bm01 : OUT std_logic_vector(BM_Width - 1 DOWNTO 0);
bm10 : OUT std_logic_vector(BM_Width - 1 DOWNTO 0);
bm11 : OUT std_logic_vector(BM_Width - 1 DOWNTO 0)
);
end branchmetric ;

architecture brm of branchmetric is

SIGNAL bm00_0 : std_logic_vector(Bit_Width - 1 DOWNTO 0);
SIGNAL bm00_1 : std_logic_vector(Bit_Width - 1 DOWNTO 0);
SIGNAL bm01_0 : std_logic_vector(Bit_Width - 1 DOWNTO 0);
SIGNAL bm01_1 : std_logic_vector(Bit_Width - 1 DOWNTO 0);
SIGNAL bm10_0 : std_logic_vector(Bit_Width - 1 DOWNTO 0);
SIGNAL bm10_1 : std_logic_vector(Bit_Width - 1 DOWNTO 0);
SIGNAL bm11_0 : std_logic_vector(Bit_Width - 1 DOWNTO 0);
SIGNAL bm11_1 : std_logic_vector(Bit_Width - 1 DOWNTO 0);

 

[Juanita99]

Thanks to the article, Now there is more reason to comment than ever before! Everyone should participate. I am incorporating what your wrote to our project!
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[amr ezz rashed]

it is very easy way because matlab include viterbi decoder and this is away to convert it to vhdl
just write in matlab command window
>>demos
and see demos about simulik=>hdl coder=>communication=>viterbi decoder
use matlab 2008a or higher

 

[Sachin Giri]

hi, i recently saw project report on the same topic. if you are interested for the same, i can be somewhat helpful..........:|

 

[setareh_mehr85]

I will be tgreatful if you help me, I am almost done with my coding but the big problem is the fpga board could you help in any way, I'm kind of stuck right now