[SOLVED] Delta sigma modulator with asymmetrical step sizes

[palermo]

Dear community,

I try to design a delta-sigma modulator. I have fully differential structure and the amplifier is simple folded cascode opamp w/ nMOS input devices. When I implement a sole switched cap integrator out of these, everything works very well. However, when I modify the structure into a 1st order modulator (i.e. adding ideal latched comparator and a mux for Vref switching), step sizes vary for up & down steps at the integrator output.

Where do you think I should look into?

Details:
Implemented circuits are charge based SC integrator and MOD1. A proper clocking scheme is used to reduce the charge injection (i.e. delayed and non-delayed phases are existent).


Best,
palermo

 

[adix]

Have you taken into account the extra load added by the comparator? And the kickback effect of the same? You might try to add a preamplifier in front of the comparator to reduce the kickback effect if that is causing any trouble to your modulator...

 

[palermo]

Have you taken into account the extra load added by the comparator? And the kickback effect of the same? You might try to add a preamplifier in front of the comparator to reduce the kickback effect if that is causing any trouble to your modulator...

hi,

i use d-ff from ahdlLib, which is ideal and does not load the circuit.

 

[palermo]

FYI: It was a switch problem. When I implemented ultra low resistance switches, it has vanished.