Declaration of signals in package

[kakarala]

hi
can i declare a signal in a package and assign a value to that signal in some other entity design?

 

[permute]

That feature is not synthesizable currently. You can declare a signal in a package, but the tools will not implement any assignments to the signal. Essentially, the signal can only be used as a constant.

 

[jducluzeau]

why do you want to this?
a signal represents a net or a port then. it is unique.

 

[permute]

The most common reason to want this is for debug. For example, to get /u_top/u_wrapper/u_module/g_option/u_inst/g_option_a/my_signal to connect to an LED or other interface. Its very annoying to thread a signal through a deep hierarchy, and it tends to make the code cluttered as simple modules start getting normally unused debug ports.

VHDL-2008 does support addressing a signal in another level of the hierarchy, but in this case Xilinx luckily doesn't implement VHDL-2008.


Chipscope allows an alternative to this, but has its own restrictions. Notably that it isn't in webpack.

 

[TrickyDicky]

Or in Quartus's case, just refuse to deal with the signal full stop.

From kakarala's post here, and previous posts, Im guessing he's trying to do something he shouldnt be doing, like by-passing port maps because he didnt learn digital electronics yet.