sebblonline
Newbie level 5
Hi,
I have problems using the DDR2 RAM on my XUPV5-LX110t Board. I generated it using MIG core generator (ISE 12.1 and also 12.3 recently) with VHDL sources.
1. I didnt succeed in simulating the core using the generated example design, because the ddr2 model only is available as a verilog file (ddr2_model.v) what results in a simulation error because the rest of the design is in VHDL. I used the ISE Simulator. When I generate the core with verilog sources, the simulation runs, but stops during the init phase (ACTIVATE state) of the memory controller.
2. For testing the controller on the FPGA, I instantiated it in a seperate user design which performs very simple read/write commands on the RAM. I propagated the phy_init_done signal of the controller to a GPIO LED to check, if the init phase completes successfully, what is NOT the case.
My constraints of the design should be right, I used the DDR2 constraints out of the master_xupv5-lx110t.ucf file.
I also use two SMB cables for the 200MHz clock and configured the DIP switch SW6 appropriately.
What is the correct workflow to simulate the core using ISim or testing a simple design on the FPGA?
thanks in advance
sebastian
I have problems using the DDR2 RAM on my XUPV5-LX110t Board. I generated it using MIG core generator (ISE 12.1 and also 12.3 recently) with VHDL sources.
1. I didnt succeed in simulating the core using the generated example design, because the ddr2 model only is available as a verilog file (ddr2_model.v) what results in a simulation error because the rest of the design is in VHDL. I used the ISE Simulator. When I generate the core with verilog sources, the simulation runs, but stops during the init phase (ACTIVATE state) of the memory controller.
2. For testing the controller on the FPGA, I instantiated it in a seperate user design which performs very simple read/write commands on the RAM. I propagated the phy_init_done signal of the controller to a GPIO LED to check, if the init phase completes successfully, what is NOT the case.
My constraints of the design should be right, I used the DDR2 constraints out of the master_xupv5-lx110t.ucf file.
I also use two SMB cables for the 200MHz clock and configured the DIP switch SW6 appropriately.
What is the correct workflow to simulate the core using ISim or testing a simple design on the FPGA?
thanks in advance
sebastian