DDR2 SDRAM controller

[powerstar007]

ddr2 sdram controller

Does any body have DDR2 SDRAM/ DDR SDRAM controller documentation and source code, Thanks in advance

 

[farhada]

ddr2 controller

Hi,
If you want to use it with an FPGA, you can use the one that Xilinx offers. Just use the "Core Generator" and create your own DDR2 controller.
Or if you are using the Altera, you can use the one that they offer.
Is there a reason you need the source code for it?

 

[powerstar007]

altera ddr2 controller

I dont want to implement in FPGA, Would like to check the DRAM behavioral model with the controller.

 

[farhada]

core generator ddr2

Then you surely can use any of the tools from the vendors and they give you a simulation model for their devices that you can check the behavior of the controller as well as your own model.

For xilinx check this page:
**broken link removed**

And for Altera check this page:
https://www.altera.com/products/ip/iup/memory/m-alt-ddr2_sdram.html?GSA_pos=3&WT.oss_r=1&WT.oss=ddr2

Cheers,
/Farhad

 

[powerstar007]

ddr_ddr2_sdram.zip

I just wanted to look at the way they have implemented the DDR2 controller, if you have the verilog code of DDR2 controller, can you upload them.

 

[powerstar007]

ddr2 controller with fpga

Guys, Has any body worked on the DDR/DDR2 controller. Can some one upload the code and documentation.

 

[goshka]

ddr2 sdram controll

**broken link removed**

 

[homer355]

Could you upload it again?i can't down it now.Thanks!

 

[C4Cheema]

can you please upload it again

**broken link removed**

above link is almost dead ....

 

[Seeli Powlin]

Hi,
Currently I am working with DDR2.
If anyone have ddr2 configuration codes or atleast an idea regarding how to do that, tell me.
I am using Code Composer Studio.
Already i have codes for SDRAM. But i can't get how they used that.