[SOLVED] DC loading Analysis for digital circuits

[venkataphaniendrak]

How to DC loading analysis for a digital circuit.

If we check Iih and Iil of the receivers met by the Ioh and Iol, is is sufficient.

 

[KlausST]

Hi,

Generally yes...
What does the specification say?

Klaus

 

[venkataphaniendrak]

Hi Klaus,

There is no guideline, i am jus having a doubt.

Hi,

Generally yes...
What does the specification say?

Klaus

 

[dick_freebird]

Modern circuits generally have no DC loading. This was not
the case in the days of xxTTL logic. Now loading is almost
always capacitive when you are talking logic, and affects
rise/fall times (hence delay) mostly.

Receivers as in transmission line, tend to have a highish
Zin set in design to be tolerable relative to the line
termination impedance at some declared max fanout /
party line number. For example you'll see 10K inputs
on RS-422 receivers for that 100-ohm system, which
says FO=10 is 10% error, which ought to be acceptable
as regards ringing / staircasing).

You probably want to work toward a VOH>VIH, VOL<VIL
loaded analysis as input sensitivity / noise margin specs
tend to be on a voltage basis.