counter VHDL PAR problem

[vinodkumar]

counters in vhdl

Hi ALL
iam implementing the simple counter VHDL code,behavioral simulation doing well.but PAR simulation getting glitches.
Can any one help?

warnings in MAP:LIT:243 - Logical network N5 has no load.
LIT:395 - The above warning message base_net_load_rule is repeated 1 more times for the following (max. 5 shown):
N6
To see the details of these warning messages, please use the -detail switch.

 

[m_kartik]

explain entity counter vhdl

Can you post your coding.

 

[vinodkumar]

event counter vhdl

here is the code written:

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clock,reset,temp)

begin
if(clock='1' and clock'event)then
if (reset='1')then
temp <= temp+"0001";
else
temp <="0000";
end if;
end if;
count <= temp;
end process;

end Behavioral;


Heh simulation working,post translate sim working..

Added after 15 minutes:

Here is aynchronous attempt which i did problem once again with PAR simulation,here is the code....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clock,reset,temp)

begin

if (reset='1')then
temp <="0000";
else if(clock='1' and clock'event)then
temp <= temp+"0001";
end if;
end if;
count <= temp;
end process;

end Behavioral;

Added after 56 minutes:

glitches observed in

temp_3_dxmux_1

/temp_3_dymux_2

 

[venkatesankalidass]

address counter vhdl

Hi vinodkumar ,

i the above code , the first is

if(clock='1' and clock'event)then

ur trying to impement sync counter , so don't put reset and counter in the sencitivity list


Regards
venkatesan

 

[FvM]

lit:243 +has no load

so don't put reset and counter in the sencitivity list

Doesn't change anything. Additional signals in the list(apart from clock) are ignored anyway in this case.

The counter actually has no glitches, when looking at each bit. But the bits change at slightly different times. Thus a decimal representation of the count value has (or seems to have) glitches. A gray counter would be the only way to represent the count value in a way, that stays consistent during increment or decrement operation, respectively is completely glitch-free.

You probably understand the problem, when you browse literature on gray counters, e. g. the wikipedia entry.