Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I want to know the way of designing a counter using both the positive and negative edgse of the clock to get output waveforms which are not of 50% duty cycle.
The suggested code isn't synthesizable cause it would require flip-flops that operate on both edges. They don't exist in FPGA or ASICs as far as I know. Also delay statements are usable in simulation only!
Various solutions for frequency dividers operating on both edges have been posted at EDAboard, I assume that you'll be able to find some of them, They are generally using positive and negative clocked flip-flops with combinational logic.
Can u please let me know some websites in Edaboard or any other websites where I can find out solutions of frequency dividers operating in both the edges?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.