counter design with negative and positive edge

[ASIC_intl]

HI

I want to know the way of designing a counter using both the positive and negative edgse of the clock to get output waveforms which are not of 50% duty cycle.

Regards

 

[gliss]

You can try inserting buffers to get the output data away from the clock.

 

[kumarghz]

can you further describe about wht design you want?

 

[sree205]

how about this following code? does this meet ur spec. ?

`define width 2
`define delay 2

module example(clk,rst,counter);

input clk,rst;
output [`width:0] counter;

reg [`width:0] counter;

always@(clk)
gen_clk = #`delay clk;

always@(posedge clk or negedge gen_clk or negedge rst)
if(!rst)
counter <= 'b0;
else
counter <= counter+1'b1;

endmodule

 

[FvM]

The suggested code isn't synthesizable cause it would require flip-flops that operate on both edges. They don't exist in FPGA or ASICs as far as I know. Also delay statements are usable in simulation only!

Various solutions for frequency dividers operating on both edges have been posted at EDAboard, I assume that you'll be able to find some of them, They are generally using positive and negative clocked flip-flops with combinational logic.

 

[sree205]

yes, its not a synthesizable option. it can only be used in behavioural modelling.

 

[ASIC_intl]

Hi FVM

Can u please let me know some websites in Edaboard or any other websites where I can find out solutions of frequency dividers operating in both the edges?