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Cortex-M3/M0: NVIC, how to configure level or pulse trigger interrupt (by software?)

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riscy00

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I have read the ARM document about Cortex-M3 (or M0) and it say it can be used as level sensetive or pulse (edge) interrupt within the NVIC controller. The problem that it rather vague on how to do this, if this is done by software.

I fails to see any kind of register within the NVIC or such that control the type of the interrupt (to select edge or level by adjusting the register bits). So something must be done by software within handler but again it vague in this field.

I like to hear anyone having a way to make it edge or level trigger interrupt by software.

Please demonstrate within the handler code (if this control it) that the make it detect for level or pulse.

If this is level detect, I can hold interrupt active and disable by the handler, until restore by external code for which it re-excute the interrupt. This is what I'm trying to do, but it will not work if this is pulse detect type.
 

The interrupt for GPIO is shared with EINT3 then a read of IOIntStatus bit0 and bit1 and IO0IntStatR/IO0IntStatF or IO2IntStatR/IO2IntStatF can provide the exact source of the interrupt
The interrupts are controlled by IO0IntEnR/IO0IntEnF and IO2IntEnR/IO2IntEnF for each individual pin.

Alex
 
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