core generator in xilinx-reg

[arunshanmugam46]

hi all,
when i use coregen to create a block ram and synthesise the code using xilinx ise 10.1 i get the following errors:


Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'yut' with type 'blk_mem_gen_v2_7' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol 'blk_mem_gen_v2_7' is not
supported in target 'xa9500xl'.

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 1
Number of warnings: 0


One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "testertop.bld"...

Process "Translate" failed
how to rectify these errors

 

[barry]

I've run into this problem when coregen sticks some of its files into a different folder than the synthesis wants to see. Try copying your ngc and/or edif files from coregen to the directory where your other sources sit. I'm not sure exactly WHERE they want to be.

 

[guitarguy12387]

Yup, this is almost always the case that an .ngc is not where it should be. Usually try re-generating the core can help. In your case, though, the device chosen doesn't support that core... just like the error message said. Pick a different part.

 

[barry]

In your case, though, the device chosen doesn't support that core

Ah, right. Make sure you always read the ENTIRE error message, like I didn't.