Converting ADC samples to an appropriate fixed point format

[cmos babe]

Hi , I have a system with an ADC that recieves an analog signal that may have values in the 0 - 5 V range. The signal must be filtered in the digital domain. My question is how should the 8 bit samples be converted to match the format of the filter coefficients?

Thanks.

 

[rsrinivas]

Re: Converting ADC samples to an appropriate fixed point for

Hi
Even i am working on a same project.for this u need to design the filter then quantize it to the required specifications. Note that as u decrease the no of bits/sample ur round off (due to quantization)noise power spectrum gets worse.
so donot quantize to 8 bits.try 16 bits.If u r familiar with Matlab try fdatool.
If u get anything helpful pls do share it.

cheers
srinivas

 

[cmos babe]

If I use the ADC samples right away with the quantized filter coefficients the calculations will be wrong. For example let's say I'm using fractional fixed point to represent the coefficients then an ADC sample will have a different meaning. For example a 1111 1111 sample is 255 in decimal and represents 4.9 Volts , while a 1111 1111 coefficient is 0.9 (assuming it's unsigned for simplicity). So what I need to know is what the most appropriate approach is to convert the ADC raw samples to a format that I can use in my calculations and get correct results.

 

[echo47]

After reading your first message, my answer would have been this (assuming your signal processing uses floating point arithmetic in C):

unsigned char ADC_value;  /* 0 to 255 represents 0.0 to 5.0 volts */
double signal_voltage;
...
signal_voltage = 5.0 / 255 * ADC_value;

But after reading your second message, I'm confused what you are trying to do.

 

[cmos babe]

Re: Converting ADC samples to an appropriate fixed point for

After reading your first message, my answer would have been this (assuming your signal processing uses floating point arithmetic in C):

unsigned char ADC_value;  /* 0 to 255 represents 0.0 to 5.0 volts */
double signal_voltage;
...
signal_voltage = 5.0 / 255 * ADC_value;

But after reading your second message, I'm confused what you are trying to do.

I want to implement a digital filter on an FPGA. So, Coefficients and ADC samples of the input signal will be represented as fixed point numbers. But the ADC samples when first recieved have a different dynamic range (0-255) and scaling (5/255) from those of the filter's coefficients which are (at the moment) represented in 8-bit fractional fixed point format. So I think that I need to change the way the samples and/or the coefficients are represented so that the output values of the filter are correct.
That's what I'm trying to do/understand.

Thanks and regards.

 

[rsrinivas]

Re: Converting ADC samples to an appropriate fixed point for

Hi
u know the maximum and minimum values u get from an ADC.
say up to 5 volts. Know what type of quantiztion ur ADC uses to sample these.
once u know the maximum range u can allocate that many bits to ur fractional and mantissa part and proceed.
ex.
sayur maximum and minimum values are 5 and 0. u need 3 bits for the mantissa and the remaining 5 bits are for the fractional part(8 bit format as u said).
If i am right what u r confusing is how does the filter know what format the data is coming.for that u need to quantize ur filter also.ur HDL need to be properly coded for that.Even i am doing the same thing. i am done with the filter(Butterworth bandpass order 6 SOS)and now doing the interfacng logic for that.
If u really think this what i have understood is wrong pls do correct me so that i can rectify as it may cause problems later.

cheers
srinivas

 

[echo47]

I normally use integer processing in FPGAs, not fixed-point. I would simply left-shift the 8-bit input data to better fill my Xilinx FPGA's 18-bit data word (but beware of filter overflow), and feed that into the filter. The filtered output will have a scaling factor associated with it (including the ADC factor, the left-shift factor, and the filter's gain), but I don't worry about it until after all the signal processing is done. I usually apply the scaling factor (one multiplication) in the system's display/output routine (perhaps a C program running a user interface).

 

[rsrinivas]

Hi echo
wat u say is like this
say you have 24 bits u shift it left by 6 bits(to meet 18 bits constraint in the fpga u r using) and later multiply the result by 2^6. is it wat u do?
don't u tell the filter the formats of inputs coeff and outputs.???

 

[echo47]

Right-shift, not left-shift.

Yes, I could input 24-bit integer data, right-shift it by 6 bits, feed it through an 18-bit unity-gain filter, and then left-shift it by 6 bits to produce a 24-bit integer output. The overall input-to-output would have unity gain.

When I design a filter in HDL, I usually hand-code it, choosing the bit widths of every register, accumulator, and coefficient ROM. They are ordinary 2's compliment integers, no special formats. If there's a scaling factor associated with the data, I deal with it after all the FPGA signal processing is done.

 

[rsrinivas]

ya right shift.
have you designed a filter in that way in HDL and got the output matching??
hey i have one problem. once you get the filter output(say input is from a test bench to the filter in HDL like impulse step and AWGN).How do get this simulation output into Matlab or so to plot it and verify it.
any suggestions??

cheers
srinivas

 

[echo47]

Yes, I've built many filters that way.

I haven't tried using MATLAB for testing the HDL results. I usually design the filter math in MATLAB, implement it in Verilog, check it's behavior at a few spot frequencies in ModelSim, and then download the design into an FPGA on my bench and sweep it with a network analyzer.

 

[rsrinivas]

Hi echo wat speeds have u achieved(clock speed).
I am stuck at 70 MHz and it's a damn poor speed i think. can u mail me a filter verilog code so tat i can compare my results.
thanks i advance.
srinivasrangaswamy@yahoo.co.in

cheers
srinivas

 

[echo47]

70 MHz may be fast or slow depending on which chips you are using. If you tell us your chip type, I'm sure someone can point you to a good application note from Xilinx or Altera or whoever. Or maybe you can show us your code and we can help you improve it. Careful pipelining is usually the solution.

I did a variety of 18-bit FIR filters in Xilinx Virtex-II -4 chips (the slowest cheapest grade). They run comfortably at 150 MHz per tap. I could probably have pushed them closer to 200 MHz (which is about the limit of the Block RAMs and multipliers), however for me the extra speed wasn't worth the increased design time and place-route run time. I also played around with a Spartan-3, and it had roughly similar speed. I'm moving on to Virtex-5 (hopefully) and Spartan-3E.

I don't have a clean stand-alone filter to show you, sorry. My filters are only a few lines of code, but they are interleaved with other processing steps that are company proprietary.