convert vhdl to verilog code

[funjoke]

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DataMEM is
port(datain,address: in std_logic_vector(31 downto 0);
CLK,wrtenb,readenb: in std_logic;
dataout: out std_logic_vector(31 downto 0));
end DataMEM;
architecture behav_DataMEM of DataMEM is
type MEM_type is array(1023 downto 0) of std_logic_vector (7 downto 0);
signal data_mem : MEM_type;
begin
process(CLK,address)
begin
if (CLK' event and CLK='1' and wrtenb='1') then
data_mem(conv_integer(address)+3) <= datain(31 downto 24);
data_mem(conv_integer(address)+2) <= datain(23 downto 16);
data_mem(conv_integer(address)+1) <= datain(15 downto 8);
data_mem(conv_integer(address)) <= datain(7 downto 0);
end if;
if (readenb='1')then
dataout(31 downto 24) <= data_mem(conv_integer(address)+3);
dataout(23 downto 16) <= data_mem(conv_integer(address)+2);
dataout(15 downto 8) <= data_mem(conv_integer(address)+1);
dataout(7 downto 0) <= data_mem(conv_integer(address));
end if;
end process;
end behav_DataMEM;




can anybody help

 

[bigdogguru]

There are several VHDL to Verilog Converters Available:

**broken link removed**

 

[funjoke]

but i cant use this to convert it ,i wan the direct address to download the tools for converter ,,, x -tek i have downloaded but cant convert it well