taoshen
Junior Member level 1
in a vhdl file, there are the two following expression:
===========================
variable tt : std_logic_vector(7 downto 0);
...
tt := (others => '-' );
if ( exp1 and not exp2 )
===========================
how to express the same meaning of "-" and " and not " with VerilogHDL.
===========================
variable tt : std_logic_vector(7 downto 0);
...
tt := (others => '-' );
if ( exp1 and not exp2 )
===========================
how to express the same meaning of "-" and " and not " with VerilogHDL.