Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

confusion about generated clock when specify cts

Status
Not open for further replies.

Kaisia

Junior Member level 3
Joined
Sep 29, 2010
Messages
29
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,411
when i specify cts information in encounter.
i get some information just like:

Input pin top_inst/clk_ctrl_inst/div_reg/CP (stdcell SDFF) doesnt have timing arc to go out.

what is the exact meaning?

ps:this reg is used to generate a divided clock, and it has been specified as a generated clock. additionally, this clock doesnt has any sink in my top module. it would go out to get used in other place.
 

If i understood correctly you are trying to build the CTS from pll_clk and this clk goes to divider (flops) and output of those divider will act as clock .
Then
1.why r u building the CTS from root pin to this divider flop if there is no other sink to the root clock except divider flop.
If there are other sinks to the root clk then you can specify divider flop CK pin as leafpin in your CTS spec file.
2. might be you can specify this divider flop as through point ----not a good idea
 

If i understood correctly you are trying to build the CTS from pll_clk and this clk goes to divider (flops) and output of those divider will act as clock .
Then
1.why r u building the CTS from root pin to this divider flop if there is no other sink to the root clock except divider flop.
If there are other sinks to the root clk then you can specify divider flop CK pin as leafpin in your CTS spec file.
2. might be you can specify this divider flop as through point ----not a good idea

it's already recognized as a through pin by tools (because it's defined as a generated clock).
my confusion is why report it no timing arc from the very reg input pin CK. the divided clock will apply for another place which no in my top.
 

r u specifying the root clk as AutoCTSRootPin ?
As far i know tools will not treat flop as through point by default ...
 

r u specifying the root clk as AutoCTSRootPin ?
As far i know tools will not treat flop as through point by default ...

when that point( the dff output Q) is defined as a generated clock, the backend tool will recogize it and treat it as a through pin.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top