oAwad
Full Member level 2
I'm attempting to design a circuit that takes 16 9-bit inputs, get the maximum, and then subtract each input from the maximum. Latency is not a constraint, however I'm concerned about throughput and area. Naively, I need a comparator tree of 15 comparators to get the maximum, and 16 subtractors to subtract each input from the maximum. Is there an efficient way to reuse the comparators to do the subtraction ? (especially if I use say 1 to 4 comparators only with an FSM to reduce my area). Can I combine both functionalities in one circuit efficiently?
Give me your thoughts
Give me your thoughts