Comparator toggle frequency relationship to the rising and falling time

[Junus2012]

Hello,

I am reading the data sheet of TLV9022 comparator from Texas Instruments,

I can't understand or correlate how the comparator has fast rising and falling time of 3 ns each, while its toggle frequency is only 3 MHz for the same test condition of overdrive voltage

Thank you

https://www.ti.com/lit/ds/symlink/tlv9024-q1.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1666203914932&ref_url=https%253A%252F%252Fwww.mouser.de%252F

 

[KlausST]

Hi,

the one is for push-pull output, the other for open_drain output.
The rise time of the open drian will be much higher compared to the push-pull one.

Klaus

 

[danadakk]

The prop delay L-H and H-L + Tr + Tf = ~ 115 + 150 + 3 + 3 = ~ 271 ns = ~
3.7 Mhz, and those are typ values, not over T and V and Cload.....


Regards, Dana.

 

[Junus2012]

Thank you very much friends for your help,

the one is for push-pull output, the other for open_drain output.
The rise time of the open drian will be much higher compared to the push-pull one.

Yes you are right, I agree with you and I can digest this value for this reason.

The prop delay L-H and H-L + Tr + Tf = ~ 115 + 150 + 3 + 3 = ~ 271 ns = ~
3.7 Mhz, and those are typ values, not over T and V and Cload.....

I had a previous conversation about a similar point, what I understand is when you use the comparator for comparing inputs and give the output to the next stage, then propagation delay should not effect the toggling frequency.

However, if you use the comparator with a closed loop, like to build a relaxation oscillator, then this delay will be feedback to the input and hence need to be added and will be a limiting value for defining the maximum frequency of oscillation of the comparator relaxation circuit.

Thank you once again

 

[danadakk]

I had a previous conversation about a similar point, what I understand is when you use the comparator for comparing inputs and give the output to the next stage, then propagation delay should not effect the toggling frequency.

Think in simplistic terms . If Prop delay were >> input freq what possible state could
the output ever achieve ? The ouput would never change. Take your square wave generator
and drive a simple gate. You will see output change from square to tri (just rise and fall time)
to nothing as you exceed its prop delay.

What is Propagation Delay

Learn about Propagation Delay in your FPGA and ASIC. How it affects timing errors and timing analysis. Learn how to fix long propagation delay.

nandland.com

Maximum Clock Frequency - VLSI Master

Verificationmaster

vlsimaster.com

https://www.cs.wustl.edu/~roger/260M.f13/CSE260M-Timing.pdf

Note gate and comparator can be used interchangeably for the purposes of this discussion.


Regards, Dana.

 

[Junus2012]

Think in simplistic terms . If Prop delay were >> input freq what possible state could
the output ever achieve ? The ouput would never change. Take your square wave generator
and drive a simple gate. You will see output change from square to tri (just rise and fall time)
to nothing as you exceed its prop delay.

What is Propagation Delay

Learn about Propagation Delay in your FPGA and ASIC. How it affects timing errors and timing analysis. Learn how to fix long propagation delay.

nandland.com

Maximum Clock Frequency - VLSI Master

Verificationmaster

vlsimaster.com

https://www.cs.wustl.edu/~roger/260M.f13/CSE260M-Timing.pdf

Note gate and comparator can be used interchangeably for the purposes of this discussion.


Regards, Dana.

Dear Dana,

In the examples you showed, I do agree with you on the restriction of the PD to the maximum clock frequency. It is true here because if you look at the examples, they are master/slave flip flop, ideally both they should be synchronised to the same clock period, otherwise if due to PD is higher than the clock period then they will not run correctly.

In this case, if you are driving a single gate and looking to its output, here the PD will not hurt you, and if you see a slewing signal then it should be due to the rising and falling time characters of your gate that is in this situation is slower than the clock edges rate.

Again, my I mean above is a single gate. However, if you take a simple flip flop, the PD will play of defining the maximum frequency since it is has feedback that brings the PD in to the account.

 

[danadakk]

But do we agree if we drive a 1 us (Tpdh + Tpdl + Tr + Tf + ....) comparator with a 10 Mhz signal
we will not see the output toggle ?

Note there is a small signal effect that comparator overdrive comes into play, but
that only adds time to the problem.


Regards, Dana.