combinatorial logic coding style question

[Spud]

Hello all,

I am new to here. I've read some threads that very helpful to me and I'm confused about a question.
As for combinatorial logic coding, the following coding style is suggested instead of assignment statements. Please see below simple clk switch procedure:
------------------------------------------------------------------
always @ ( func_en )
begin
if ( func_en )
begin
output <= clk1;
end
else
begin
output <= clk2;
end
end
------------------------------------------------------------------

instead of

------------------------------------------------------------------
wire output = func_en ? clk1 : clk2;
------------------------------------------------------------------
My question is that should clk1 & clk2 need to be added to sensitivity list ? because
Quartus always warns me about that.

My another question is about combinatorial logic coding style, too.
Please explains to me if the following three procedure generates the same
logic or not? Which coding style is better? thanks for reading this post and
for your replies.
-1. --------------------------------------------------------------
wire output_clk = clk1 ^ clk2;
------------------------------------------------------------------
-2. --------------------------------------------------------------
always @ ( clk1 or clk2 )
begin
output_clk = clk1 ^ clk;
end

-3. --------------------------------------------------------------
always @ ( clk1 or clk2 )
begin
if ( clk1 & clk2 )
begin
output_clk <= 0;
end
else if ( clk1 & ~clk2 )
begin
output_clk <= 1;
end
else if ( ~clk1 & clk2 )
begin
output_clk <= 1;
end
else
begin
output_clk <= 0;
end
end
------------------------------------------------------------------

 

[pramodm]

yhaaaaaaa U need to add clk1 and clk2 to ur sensitivity list otherwise the synthesis tool infers latch for output because of the changes in clk1 & clk2 not evaluate the circuit operation

 

[amitgangwar_vlsi]

if you do not write clk1 and clk2 in sensitivity list.. then hardware generated will be right and synthesis will be right. but in simulation you will get the wrong out put. and your synthesis and simulation result will be differ.

there are some constructs which are ignored by the synthesis tool.