nicklas_a74
Member level 1
code check do 254 problems, vhdl
Hi
I have a problem with a vhdl design that have been code checked
with do254.
* I have some signals between components as signal(16 downto 0) which
I internally use as new_signal <= signal (16 downto 7) in a component
and not using the other bits in the signal(6 downto 0)
How to solve this error and keep the signal(16 downto 0)
as it is? I want to use some of the bits from the signal only.
Hi
I have a problem with a vhdl design that have been code checked
with do254.
* I have some signals between components as signal(16 downto 0) which
I internally use as new_signal <= signal (16 downto 7) in a component
and not using the other bits in the signal(6 downto 0)
How to solve this error and keep the signal(16 downto 0)
as it is? I want to use some of the bits from the signal only.
