CMOS implementation of bias circuits

[calculus_cuthbert]

Hi

I am trying to design a CMOS class AB output buffer. I have attached a schematic. I have used two voltage sources (Vbias1 and Vbias2) to bias the transistors in the right region for a class AB operation.

Could you someone please suggest how to realize these voltage sources with transistors? How do I actually design these bias voltages?

Thank you.

 

[diemilio]

Hi again calculus_cuthbert,

I've done this before using diode connected NMOS and PMOS transistors which you can bias with DC current sources at the top and bottom. It works pretty well, the only drawback is that the voltage is not process compensated, so if you want to minimize variation keep in mind that you should use long transistors. Now, if that is not good enough then you will have to include some sort of control to adjust the bias current through the transistors to get the desired voltage.

Hope this helps,

diemilio

 

[calculus_cuthbert]

Hi Diemilio,

Thanks for the quick response. I didn't quite understand how to do it. Do you think you could draw a schematic to show me?

Thank you

 

[diemilio]

Oops, sorry, In my case the DC voltage sources had the opposite polarity. For your case you could use an NMOS source follower for Vbias1 and a PMOS source follower for Vbias2.

diemilio

 

[calculus_cuthbert]

Hi Diemilio,

I understand what you suggested. But with that implementation won't the PSRR become worse because now there is a path straight from the supply.

Thanks

 

[diemilio]

Worse than what??

diemilio

 

[calculus_cuthbert]

I guess I meant the PSRR would be bad.. is that right?

Added after 5 hours 35 minutes:

Hi Diemilio,

Could you please take a look at this schematic that I have attached?

I am facing problems of phase margin. The output transistors are huge FYI. But when I had used ideal voltage sources I had good phase margin. When I replaced them with source followers the phase margin becomes very bad and the circuit is no longer stable.

Could you please let me know what is causing this? Is the source follower the cause? And how should I fix it?

Thank you.

 

[diemilio]

When you say "I have phase margin problems" how bad is it?? Do you have an output cap?? where is your dominant pole and where is the second pole kicking in??

diemilio

 

[calculus_cuthbert]

Hi Diemilio,

I could solve the stability problems. I had to put a capacitor at the output node of the OTA and I sized the source followers so that the non dominant pole was pushed out.

Thanks

 

[diemilio]

I'm glad you took care of the problem.

Good luck with the rest of the design.

diemilio