Clock muxing done on an FPGA

[shaiko]

I have a system with 2 clock inputs. I want the user to be able to choose which clock to use (with external pullups connected to the clock selector line).

I know that the below gated clock is bad practice when done on an FPGA.

selected_clock <= first_clock when clock_seclector = '1' else second_clock ;

process (selected_clock) is
begin
   if rising_edge (selected_clock) then
      Q <= D ;
   end if ;
end process ;

How can the above "be done the right way" on an FPGA ?

 

[mrflibble]

By using a global clock mux?

Check your favorite documentation on for example a BUFGMUX.

lazy google hit: https://www.scribd.com/doc/48214926/28/BUFGMUX