vtbvtb
Newbie level 3
Hello,
I have a problem with logic of case statement in vhdl. I wonder is the variable that selects the case condition can be changed within the statement. To clarify:
When I tried to synthesize a code with that algorithm, it displays an error. What is the problem here? Can't I change the variable within the case? Or the problem is about the if statement in the case?
If anyone can help, I'll appreciate it.
I have a problem with logic of case statement in vhdl. I wonder is the variable that selects the case condition can be changed within the statement. To clarify:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 process(clk) variable aaa: std_logic_vector(2 downto 0):="000"; case aaa is when "000" => if () then something end if; aaa := aaa+1; when "001" => if () then something elsif () then somethng something end if; aaa := aaa+1; when others => -- sequential statements end case ; end process;
When I tried to synthesize a code with that algorithm, it displays an error. What is the problem here? Can't I change the variable within the case? Or the problem is about the if statement in the case?
If anyone can help, I'll appreciate it.
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