change variable in case statement

[vtbvtb]

Hello,

I have a problem with logic of case statement in vhdl. I wonder is the variable that selects the case condition can be changed within the statement. To clarify:

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Code VHDL - [expand]
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process(clk) 
 
variable aaa: std_logic_vector(2 downto 0):="000"; 
 
case  aaa  is 
 
    when  "000"  => 
      if () then 
        something 
      end if; 
      aaa := aaa+1; 
 
    when  "001" => 
         if () then 
             something
         elsif ()  then
              somethng
        something 
      end if;
      aaa := aaa+1; 
 
    when others => 
      -- sequential statements 
 
end   case ; 
 
end process;

---

When I tried to synthesize a code with that algorithm, it displays an error. What is the problem here? Can't I change the variable within the case? Or the problem is about the if statement in the case?

If anyone can help, I'll appreciate it.

 

[barry]

I can't give you a definitive, scholarly answer, but it just seems plain wrong. It smells like recursion. I'm not sure this would work for signals either, but remember that variables are assigned 'instantly' (as opposed to signals).

 

[vtbvtb]

Thank you for the reply, I also tired signals but didn't work. I know variables are assigned instantly but when a "case" is true, other "case"s are not checked(as far as I know) so the variable aaa should change in the next execution of the process(at least that's what I thougt when I wrote the code) I'm used to java, c# etc. programming languages, so I have diffuculties in "thinking in a HDL"

 

[barry]

The main thing with HDL is to remember it's a HARDWARE description. That's where it differs greatly from pure software. Think about the actual hardware that will result from your code. (A case statement is a little difficult to visualize in hardware)

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I'm not sure what you're really trying to do, but maybe you can use one variable(call it x) for the case statement, and inside your case statement assign values to a different variable(call it y). Then assign y to x outside of the case statement.

 

[TrickyDicky]

how about posting the real code and the real error.

posting some example that has nothing wrong with it (other than not really being synchronous because you forgot the if rising_edge(clk) then bit) and then saying "I have error, fix plz kthxbye" is not the best way to get help.

 

[vtbvtb]

how about posting the real code and the real error.
saying "I have error, fix plz kthxbye" is not the best way to get help.

I couldnt post the real code since if-statements are long, complicated and include variables that would only confuse you, I would need to write paragraphs to explain what their purpose is, (also my company does not let me share any "real" code). But the pseudocode is just the above one. Thanks anyway.

 

[TrickyDicky]

I dont care what the purpose is, and I promise you variables do not confuse me.
You could at least post what the error was. The code you posted is pretty useless, and would not cause an error.

 

[vtbvtb]

then here is the code:

PROCESS (h_position, v_position)
variable cnt : std_logic_vector(3 downto 0 ):="0000";
variable decimalcnt: std_logic_vector(3 downto 0):="0000";
BEGIN 
IF ((hareketsiz_hedef > "000") AND (h_position >= YK4) AND (h_position < YK4+YB4) AND (v_position >= DK4) AND (v_position < DK4+DB4)) THEN
y <= GS4 & "00"; 
cr <= CR4 & "00"; 
cb <= CB4 & "00"; 
ELSIF ((hareketsiz_hedef > "001") AND (h_position >= YK5) AND (h_position < YK5+YB5) AND (v_position >= DK5) AND (v_position < DK5+DB5)) THEN
y <= GS5 & "00"; 
cr <= CR5 & "00"; 
cb <= CB5 & "00"; 
ELSE 
if ( f='1') then
case1: CASE cnt IS
WHEN "0000" =>
IF ((hareketsiz_hedef > "000") AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010001100") AND (v_position >= "0110100110") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND (h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101110"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
ELSIF((hareketsiz_hedef > "000") AND(h_position >= "1010001100") AND (h_position < "1010010010") AND (v_position >= "0110100100") AND (v_position < "0110101100")) THEN
y <= "1110101100"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
cnt := cnt +1;
WHEN "0001" =>
IF((hareketsiz_hedef > "000") AND(h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101110"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
cnt := cnt +1;
WHEN "0010" =>
IF ( (hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000") AND (h_position >= "1010001010") AND (h_position < "1010001100") AND (v_position >= "0110101010") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND(h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101010")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
cnt :=cnt+1;
WHEN others => null;
END CASE;
case2: CASE decimalcnt IS
WHEN "0000" =>
IF ((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1001111101") AND (v_position >= "0110100111") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010000011") AND (h_position < "1010000101") AND (v_position >= "0110100111") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
ELSIF((hareketsiz_hedef > "000")AND(h_position >= "1001111101") AND (h_position < "1010000011") AND (v_position >= "0110100100") AND (v_position < "0110101100")) THEN
y <= "1110101100"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
WHEN "0001" =>
IF ((hareketsiz_hedef > "000")AND(h_position >= "1010000011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110101110"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
WHEN "0010" =>
IF ( (hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000") AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101010") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100110") AND (v_position < "0110101010")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
WHEN "0011" =>
IF ((hareketsiz_hedef > "000")AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100110") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
WHEN others =>
null; END CASE; end if; 
END IF;END PROCESS;

Now I got rid of the error and the code is implemented on fpga but does not work in the way it is intended. What I'm trying to do is displaying a counter on the screen. "cnt" should count from 0 to 2 where "decimalcnt" should stay 0. (next, I'll also update it but not yet) The only output I get now is a "0" on pixels where decimalcnt shopuld appear(it's correct) but I see nothing for "cnt", not even a "0". So, the first case statemnt is not working.

 

[BradtheRad]

This statement:

if ( f='1') then

is on the line before your first CASE:

case1: CASE cnt IS

The keyword 'if' is not capitalized. Nor is 'then'. However the same keywords are converted to capitals in the rest of your code.

Is this an error?
Is it something that would cause an error?
Or would cause non-execution of your first CASE?

 

[alexan_e]

VHDL is not case sensitive so an if/then works the same as IF/THEN

The code formatting is kind of a mess...

 

[BradtheRad]

VHDL is not case sensitive so an if/then works the same as IF/THEN

The reason it caught my eye is because I work in BASIC programming environments which automatically convert any keyword to all caps.

I thought maybe this language does it too. Because I see the other keywords are all caps (except in just a couple spots).

I seem to remember a few times, when a line of my code contained a keyword, and it did not turn to all caps. It generated an error. Yet it was not misspelled.

I believe it must have gotten some invisible character in it somewhere, somehow.

I seem to remember a few occasions where I've had to type an entire line again, before it would behave. Never figured out what was wrong with my previous try.

if ( f='1') then

The '1' is in single quotes. Is this something that might cause an error? I don't see another occurrence where a number is inside single quotes.

 

[alexan_e]

a bit constant is written with a single quote '1'
a vector constant is written with double quote "101010"

Although your effort to help is welcome you are not familiar with VHDL so it would be difficult to provide a solution.
I would suggest to let more experience users reply to this.

 

[BradtheRad]

Also, looking at this way of exiting:

WHEN others =>
null; END CASE; end if;

I'm not familiar with VHDL but I believe this looks like it's ending a conditional tree within a conditional statement. This can lead to errors, or a buildup of loops that results in an overflow.

 

[TrickyDicky]

Like alex said - if you dont understand VHDL - dont try and help. The null statement just means "do nothing".

But there are some serious problems with this code. Either your company didnt hire you for your VHDL skills or somehow you managed to blag your way in. There are several key problems:

1. Where is the clock? counters without clocks are basically not going to work.
2. You're missing hareketsiz_hedef from the sensitivity list.
3. Why are you assigning the Y Cr and CB values inside both case statemnts? Asside from the fact that they will be created with latches because you didnt assign them in all paths, the 2nd case statement will override the first if assignments in both are taken.

You still didnt post the error.
And I assume you've fully testbenched this design? where is the testbench code?

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Oh and PS it is not the best formatted and has the worst comments Ive ever seen.

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Oh And - where are the assignments to decimalcnt