Change signal value in the middle of other

[timsanr]

Hi,
I need to send signal like here (first is clock): but the middle should rise there where is yello cursor. If that down signal is 2 x longer than clock, so the second signal must change value on falling_edge of clock. Is it possible? Or I need to decrease twice lower signal frequency to have another rising_edge clock in the middle?

 

[FvM]

Performing all actions on one clock edge is the preferred way to design synchronous logic. Utilizing both edges is generally possible, but watch your step.

 

[timsanr]

So could you tell me please some hint, how to do it on one clock edge?

 

[FvM]

On one clock edge means doubling the input clock, as you already mentioned. There's no third way.

 

[timsanr]

Thanks a lot.

 

[FvM]

There's an option to make the output signal by combining output of rising edge clocked registers and the clock itself, but it's at risk to generate glitches. Thus it's the worst method in my opinion.