pwq1999
Member level 2
verilog case
i wonder if the case statement without the parallel directive,is it synthesized to a priority case?
and if a full case directive, is it also synthesized to a priority case?
is there a way to make the synthesizer to synthesize the code into parallel case without any directive in the verilog code ?
thanks in advance!
i wonder if the case statement without the parallel directive,is it synthesized to a priority case?
and if a full case directive, is it also synthesized to a priority case?
is there a way to make the synthesizer to synthesize the code into parallel case without any directive in the verilog code ?
thanks in advance!