HardwareChap
Junior Member level 1
I would like to hold the logic level on pin 'D' of a D-type Latch high for 100 ns after the pulse driving it has gone to zero. The pulse will be from a NOT gate, 3 V and will be high for 0.5 ms (min). I was thinking of using a series R and C to ground to hold it above the logic threshold of 2 V for 100 ns. I know that \[\tau\] = RC. How do I calculate suitable values so that the voltage on the 'D' pin is > 2.1 V for at least 100 ns after the falling edge of the input pulse?