rokyslash
Newbie level 1
I am a beginner when it comes to verilog and i have found this 32 bit multiplier code(using CSLA logic:it seems, thats what a friend of mine said). Is there a way to reduce the code: i mean by using for loops or any other method. I am doing this for my academic project and i need some expert help if there is a way i can reduce this.
P.S I am new to such forums and stuff, so please forgive me if i am posting things in a wrong way or anything.
Here is the code attached and it has simple AND gate,half and full adder modules in this.
P.S I am new to such forums and stuff, so please forgive me if i am posting things in a wrong way or anything.
Here is the code attached and it has simple AND gate,half and full adder modules in this.