can u explain about holding voltage of ESD

[tomato]

hi~

I don't know why lower hold voltage is good after snapback.

thanks in advance.

 

[DenisMark]

With lower hold voltage ESD devices dissipate much less power. As you know P=I*V. So this device can conduct much more current before thermal breakdown. That is why reverse breakdown diodes have very weak ESD protection capability.

 

[hung_wai_ming@hotmail.com]

As what DenisMark said,
P=V*I, where V is your holding voltage.
Different devices have different Vhold after snapback, so P is different and you may see a larger current that can pass thru for ESD if Vhold is lower. Ppl always want to find Vhold small device to carry more current in DSM process

 

[tomato]

thanks all..

hung_wai_ming~~..what's the Ppl?

 

[prcken]

your holding voltage should be as small as possible but larger than working voltage to prevent ESD latch-up