ETRX_13
Newbie level 6
Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHDL
Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHDL
Hello Everyone,
I am doing a mini project on Perfomance Analysis of Different Adders and Multipliers using XILINX Project Navigator 14.5 to write VHDL Code for the same but in that I am getting some errors. For that matter I have asked some people but they say you cant use VHDL for clocking instead use verilog or state machines. Is it True or not plz justify me bcoz i have No Idea about it.
The problem I am facing is that I cant change to another HDL language, as I have mentioned it in my project title.
So Plz can help me out ???
Thank You,
Sincere Regards,
# ETRX_13
Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHDL
Hello Everyone,
I am doing a mini project on Perfomance Analysis of Different Adders and Multipliers using XILINX Project Navigator 14.5 to write VHDL Code for the same but in that I am getting some errors. For that matter I have asked some people but they say you cant use VHDL for clocking instead use verilog or state machines. Is it True or not plz justify me bcoz i have No Idea about it.
The problem I am facing is that I cant change to another HDL language, as I have mentioned it in my project title.
So Plz can help me out ???
Thank You,
Sincere Regards,
# ETRX_13