vjkr
Newbie level 4
Hi,
i ve this code.....................................................................................................................................................................
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.numeric_std.ALL;
entity cn is
port (A:in Std_logic_vector(1 downto 0);
B:in Std_logic_vector(1 downto 0);
C:in Std_logic_vector(1 downto 0);
clk: in std_logic;
A1,a2,a3ut Std_logic_vector(1 downto 0);
accumulator0ut Std_logic_vector(1 downto 0);
accumulator1ut Std_logic_vector(1 downto 0);
accumulator2ut Std_logic_vector(1 downto 0));
end cn;
architecture Behavioral of cn is
begin
----------------------------------------------------sequential part ------------------START
process(clk)
begin
if clk='1' then
a1<="01";
a2<="01";
a3<="01";
end if;
end process;
----------------------------------------------------sequential part-------------------END
---------------------------------------------------combinational part-----------------START
accumulator1<=a+b+c ;
accumulator2<=a+b+c ;
accumulator0<=a+b+c ;
---------------------------------------------------combinational part-----------------END
end Behavioral;
At synthesis i get
Max combinational path delay:10.610ns
I need help regarding.............
1. What about sequential part?
2. I split the design and verified sequential path only.. result: NO PATH FOUND,NO PATH FOUND,NO PATH FOUND,NO PATH FOUND. means? :/
3. whether my overall delay is SEQUENTIAL+COMBINATIONAL or max of(SEQUENTIAL,COMBINATIONAL)?
thanks
The above code is an analogy of a larger code which consists of ""components""; hence i wrote a similar code for questioning.
i ve this code.....................................................................................................................................................................
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.numeric_std.ALL;
entity cn is
port (A:in Std_logic_vector(1 downto 0);
B:in Std_logic_vector(1 downto 0);
C:in Std_logic_vector(1 downto 0);
clk: in std_logic;
A1,a2,a3ut Std_logic_vector(1 downto 0);
accumulator0ut Std_logic_vector(1 downto 0);
accumulator1ut Std_logic_vector(1 downto 0);
accumulator2ut Std_logic_vector(1 downto 0));
end cn;
architecture Behavioral of cn is
begin
----------------------------------------------------sequential part ------------------START
process(clk)
begin
if clk='1' then
a1<="01";
a2<="01";
a3<="01";
end if;
end process;
----------------------------------------------------sequential part-------------------END
---------------------------------------------------combinational part-----------------START
accumulator1<=a+b+c ;
accumulator2<=a+b+c ;
accumulator0<=a+b+c ;
---------------------------------------------------combinational part-----------------END
end Behavioral;
At synthesis i get
Max combinational path delay:10.610ns
I need help regarding.............
1. What about sequential part?
2. I split the design and verified sequential path only.. result: NO PATH FOUND,NO PATH FOUND,NO PATH FOUND,NO PATH FOUND. means? :/
3. whether my overall delay is SEQUENTIAL+COMBINATIONAL or max of(SEQUENTIAL,COMBINATIONAL)?
thanks
The above code is an analogy of a larger code which consists of ""components""; hence i wrote a similar code for questioning.
Last edited: