How is implemented a for or loop in FPGA ? Sequential or parallel

[stackprogramer]

I had a question, For or loop in Verilog how is executed? Sequential or parallel?
My qustion assignment in for executed in parallel mode?
can any one guide me??

module for_loop_simulation ();
  integer ii=0;
  reg [7:0] r_Data[5:0]; // Create reg 8 bit wide by 6 words deep.
  
  initial
    begin
      for (ii=0; ii<6; ii=ii+1)
        begin
          r_Data[ii] = ii*ii;
          $display("Time %2d: r_Data at Index %1d is %2d", $time, ii, r_Data[ii]);

        end
    end
endmodule

 

[TrickyDicky]

I had a question, For or loop in Verilog how is executed? Sequential or parallel?
My qustion assignment in for executed in parallel mode?
can any one guide me??

module for_loop_simulation ();
  integer ii=0;
  reg [7:0] r_Data[5:0]; // Create reg 8 bit wide by 6 words deep.
  
  initial
    begin
      for (ii=0; ii<6; ii=ii+1)
        begin
          r_Data[ii] = ii*ii;
          $display("Time %2d: r_Data at Index %1d is %2d", $time, ii, r_Data[ii]);

        end
    end
endmodule

All hdl is executed sequentially in a simulator.
But depending on the code, it may create parallel circuits when synthesised.

 

[stackprogramer]

Thanks very much, But depending on the code??
For example, this example code how much synthesizes? can you explain more?

Is this code equivalent another code in synthesis? what's the difference below code?

//code 1:
for (ii=0; ii<6; ii=ii+1)
 begin
  r_Data[ii] = ii*ii;
end

//code 2:
r_Data[0]=0*0;
r_Data[1]=1*1;
r_Data[2]=2*2;
r_Data[3]=3*3;
r_Data[4]=4*4;
r_Data[5]=5*5;

 

[FvM]

No difference. In the context of an initial block, both codes aren't actually synthesizing logic, only initializing variables that are acting as constants.

 

[stackprogramer]

No difference. In the context of an initial block, both codes aren't actually synthesizing logic, only initializing variables that are acting as constants.

If they are not in the initial block? they are in pos edge CLK.....
What's do it this, can you explain this case?

  always @(posedge ctrlport_clk) begin

for (ii=0; ii<6; ii=ii+1)
 begin
  r_Data[ii] = ii*ii;
end

end

 

[FvM]

As long as r_Data isn't assigned other values in other parts of the always block, it's still acting as constant. And if r_Data is never read anywhere, it will be discarded in synthesis.

Questions about HDL synthesis based on incomplete code snippets have rarely clear answers. You should at least provide a complete module with in- and outputs.