Cadence Layout problem: Poly without implant not allowed

[Beardolphinaries]

Hi, can anyone help me about this?
I am using ST 0.13um designkits in Cadence.
when I am trying to make some layout and DRC, there is an error :

' Poly without implant not allowed'.

Can anyone tell me that does this mean? Thanks a lot.

 

[forkschgrad]

Re: Layout problem

i think its the lpph layer.

 

[sandeep_torgal]

Layout problem

Check the DRC rule deck as to which layer is expected. However I dont have much idea about ST 0.13um designkits

 

[fixrouter4400]

Re: Layout problem

Hi, can anyone help me about this?
I am using ST 0.13um designkits in Cadence.
when I am trying to make some layout and DRC, there is an error :

' Poly without implant not allowed'.

Can anyone tell me that does this mean? Thanks a lot.

Hi there! - I think your DRC problem is pointing to the MOS transistor gate(poly) connection...which mean that you need to put an NPLUS extension if it is nmos over the poly layer extension..distance/overlap depend on the Design Rule Deck..likewise with the pmos you need to extend your PPLUS layer over the poly layer...and your DRC error will go away...

Cheers

 

[Teddy]

Layout problem

This is common on most TSMC PDKs. Te pcell for mos is created with the N+/P+ difusion layer, but when you want to connect ie contact M1-poly the diff layer is not there. just add it - most often you can butt the P+ - N+ diffs.

 

[protonixs]

Re: Layout problem

This is common on most TSMC PDKs. Te pcell for mos is created with the N+/P+ difusion layer, but when you want to connect ie contact M1-poly the diff layer is not there. just add it - most often you can butt the P+ - N+ diffs.

yeah teddy is right. u may put either P or N implant to the poly layer.

 

[nav_r]

Layout problem

yep dear, Teddy is right, me too using the TSMC 65 nm, we abutt both the diffusions (OD layer in TSMC), actually the implant layer defines whether the transistor is p-type or n-type, so u dont hav to do anything just extend the implant region with the OD or diffusion layer,

Or if u r using the p-cells, den just put the implant over it.

 

[yaasi]

Layout problem

it is b'cos of the pplus r nplus enclosure of poly is less than the DRC rule.
So draw one rectangle enclosing the poly as specifed by the rule.Rectangle shud be pplus for pmos and nplus for nmos.

 

[kansal]

Re: Layout problem

there is a DRC rule that poly should be enclosed by a pp layer for P-channel and with NP layer for n-channel transistor with a certain distance,which varies acc to technology...

 

[varma_cs012]

Re: Layout problem

I guess already lot's of ppl given the answer.
It's simple Either it is poly or diffusion, It should be either P type or N type.
So we should cover them with PPLUS or NPLUS.

Other wise u will get these errors. Thank you.

 

[jecyhale]

Re: Layout problem

you should add an implant layer on it to reduce the resistor.