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Cadence :Gain, Stability, Noise for Analog Circuit

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justsunny

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Dear All,

I have designed the following two-stage-op-amp (CMOS .18um technology) in cadence.
I am new in analog IC design. What are the steps to plot graphs for Gain, Stability and Noise for this circuit. Gain Bandwidth is 5M Hz and VDD= 2.5 V.

Thanks.
 

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