bhliuliu
Newbie level 1
Dear all,
I am using Synplify Premier H-2013.03-1 as synthesis tool. At the last step Map & Optimizations, it reported me that " @E:MF320 : | c_ver failed generated Verilog file ", but i do not know how to solve it., pls take me a support, thank you.
I am using Synplify Premier H-2013.03-1 as synthesis tool. At the last step Map & Optimizations, it reported me that " @E:MF320 : | c_ver failed generated Verilog file ", but i do not know how to solve it., pls take me a support, thank you.