C/Verilog code for CRC calculation for polynomials

[stay_in_chaos]

any body having the C or Verilog code for crc calculations for this polynomials

g(x) = x8 + x2 + x + 1
g(x) = x12+x10+x8+x5+x4+x3+1

if any material on crc Calculation or generation

Pls help me out
and help me soon plz

inadvancs thank you

 

[kib]

xilinx crc calculation c++

check following application note from xilinx

https://www.xilinx.com/bvdocs/appnotes/xapp209.pdf

it also has link to some perl files which can generate verilog file for crc polinomial selected by user

 

[EDALIST]

what is a crc polynomial equation

you can use this code :

files are in c and pic assembler.

 

[banjo]

crc32 equations for verilog

Below is some simple structural Verilog for one of your equations. The other one can be quickly written based on this model. Three items are most important with CRC calculations.

1. What is the CRC polynomial equation.
2. What is the CRC seed value.
3. Are there any "flush" values used when data packets are odd sizes.

Most descriptions give you item 1. Few give all the details about #2 and #3.
Be careful of the more fancy C and Verilog stuff on the web. Some of it works, lots of it is wrong. The code may generate the proper CRC for a few cases, but fails in real applications with real data.

---- Steve

//////////////////////////////////////////////////////////////////////////////////////////////
reg [7:0] crc_out;

// Verilog follows the flip-flop and XOR model commonly used
// for schematic based CRC circuits.
// Equation is :C(x) = 1 0000 0111
// C(x) = x^8 + x^2 + x + 1

assign crc_in_2 = (crc_out[7] ^ din) ^ crc_out[1];
assign crc_in_1 = (crc_out[7] ^ din) ^ crc_out[0];
assign crc_in_0 = crc_out[7] ^ din;
assign combo_crc_rst = rst || crc_rst;
always @(posedge clk or posedge combo_crc_rst)
if (combo_crc_rst)
begin
crc_out <= 8'b00000000; // The is the seed value
end
else if (enable)
begin
crc_out[7] <= crc_out[6];
crc_out[6] <= crc_out[5];
crc_out[5] <= crc_out[4];
crc_out[4] <= crc_out[3];
crc_out[3] <= crc_out[2];
crc_out[2] <= crc_in_2;
crc_out[1] <= crc_in_1;
crc_out[0] <= crc_in_0;
end

 

[chaitu2k]

Re: CRC calculation

hi

go to this website

https://www.easics.com/webtools/crctool

it is a crc tool which generates VHDL or VERILOG code for any given CRC polynomial and any databus width...its FREE....and its the best

enjoy!!

 

[vijaymails]

Re: CRC calculation

reg [7:0] crc_out;

// Verilog follows the flip-flop and XOR model commonly used
// for schematic based CRC circuits.
// Equation is :C(x) = 1 0000 0111
// C(x) = x^8 + x^2 + x + 1

Hi in this design when i convert polynomial to binary its required 9- bits, but you declared only 8 bits instead of 9.

Can u clarify me.
even for crc-32 also


FCS The CRC is calculated using the following Standard generator polynomial of degree 32:
//G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
//polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
//01234 5678 9101112 13141516 17181920 21222324 25262728 29303132
//11101 1011 0111 0001 0000 0110 0100 000 1
//
//11101101101110001000001100100000 EDB88320 Here 32nd bit position not considering...

waiting for reply..thq