FlyingDutch
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Hello,
I am trying to launch one of implementation of RISCV CPU called Briey. Here is link to this project:
http://github.com/SpinalHDL/VexRiscv
I just modified this project (generated with SpinalHDL) in Verilog. Here is ziped project (Xilinx ISE 14.7):
View attachment BrieySoCNext.zip
My changes:
1) Shortened AXI out buses
2) Added 2 clocks: AXI (50MHz) and VGA (25.175 MHz)
Now I am trying to make user constraint file (ucf) fo Mimas V.2 FPGA board (Spartan6 FPGA). Here is link to this board description:
http://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram
Projects implements without errors. I encountered dificulties with mapping DDR memory lines. The problem is that the LPDDR memory onboard has two directional data bus (16 bit wide), and Briey SOC has two one directional buses (16 bit wide) each. I mapped these buses two times in my ucf file like that:
but I am not sure if it is OK. I also got stacked widh other signals for DDR memory.
The type of DDR Memory is: 166MHz 512Mb LPDDR (MT46H32M16LF/W949D6CBH).
Here is ucf template for Mimas V.2 ucf file:
http://productdata.numato.com/assets/downloads/fpga/mimasv2/mimasv2_user_constraints_file.ucf
Could someone to help me with this point (mapping DDR memory lines)?
Regards
I am trying to launch one of implementation of RISCV CPU called Briey. Here is link to this project:
http://github.com/SpinalHDL/VexRiscv
I just modified this project (generated with SpinalHDL) in Verilog. Here is ziped project (Xilinx ISE 14.7):
View attachment BrieySoCNext.zip
My changes:
1) Shortened AXI out buses
2) Added 2 clocks: AXI (50MHz) and VGA (25.175 MHz)
Now I am trying to make user constraint file (ucf) fo Mimas V.2 FPGA board (Spartan6 FPGA). Here is link to this board description:
http://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram
Projects implements without errors. I encountered dificulties with mapping DDR memory lines. The problem is that the LPDDR memory onboard has two directional data bus (16 bit wide), and Briey SOC has two one directional buses (16 bit wide) each. I mapped these buses two times in my ucf file like that:
Code:
NET "Clk100Mhz1" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz ;
NET "Clk100Mhz2" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz ;
NET "io_asyncReset" LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; #SW1
NET "io_jtag_tms" LOC = U7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 1
NET "IO_P6[6]" LOC = V7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 2
NET "IO_P6[5]" LOC = T4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 3
NET "IO_P6[4]" LOC = V4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 4
NET "io_sdram_ADDR[0]" LOC = J7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[10]" LOC = F4 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[11]" LOC = D3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[12]" LOC = G6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[1]" LOC = J6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[2]" LOC = H5 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[3]" LOC = L7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[4]" LOC = F3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[5]" LOC = H4 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[6]" LOC = H3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[7]" LOC = H6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[8]" LOC = D2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[9]" LOC = D1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_BA[0]" LOC = F2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_BA[1]" LOC = F1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[0]" LOC = L2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[10]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[11]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[12]" LOC = T2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[13]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[14]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[15]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[1]" LOC = L1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[2]" LOC = K2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[3]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[4]" LOC = H2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[5]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[6]" LOC = J3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[7]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[8]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[9]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[0]" LOC = L2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[10]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[11]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[12]" LOC = T2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[13]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[14]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[15]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[1]" LOC = L1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[2]" LOC = K2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[3]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[4]" LOC = H2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[5]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[6]" LOC = J3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[7]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[8]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[9]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
but I am not sure if it is OK. I also got stacked widh other signals for DDR memory.
The type of DDR Memory is: 166MHz 512Mb LPDDR (MT46H32M16LF/W949D6CBH).
Here is ucf template for Mimas V.2 ucf file:
http://productdata.numato.com/assets/downloads/fpga/mimasv2/mimasv2_user_constraints_file.ucf
Could someone to help me with this point (mapping DDR memory lines)?
Regards
Last edited: