Booth multiplier problem, signal and blocks removed...

[Sniesk]

Hi, i am trying to implement a Booth multiplier in VHDL using ISE Webpack. I use a Nexys 2 500 board. This is my first project using VHDL (and FPGA in general) so there are some issues that i still do not understand.
First, i completed the project and simulated it. It worked and all went fine.
Then i tried to generate the programming file to mount it on my board but it didn't work. I got no errors, but a lot of warnings about unwanted latches, and a lot of signals being removed. In particular, the signal connecting to the input switches got removed so i can't actually input anything on the board.
I checked the map report to see that actually a LOT of signals and blocks got removed, and i don't know why.
I don't understand why it all goes well on simulation but then all gets removed.
What can i do?

 

[sunjianhuigou]

if the function simulation passed,you should excute the post simulation.
AFirstly, are you sure that u had download your program to the fpga chip sucessfully? maybe u should do another small test to check the downloading process is ok, containing hardware and software configuration.
About the Warning and signal removing showing, ISE tool will do some optimazation, it's nothing seriuos, but u should have a judge quikly.
u had passed the function simulation, maybe your coding is right, so u should pay attention to your post simulation and it's better to use the signalTap to capture the internal DFF's signals , to debug your design.

 

[Sniesk]

What is the post simulation? Anyway i'm sure the downloading on the board is correct, as i've tried some simple input output with leds and switches to ensure it worked.
i know that ISE does optimization on my project, but it really removes the majority of the signals, including those connected to input pins, so when the program is loaded the pin aren't connected and i can't input anything.
Another thing that i noticed reading the map report is that the signal that should contain the result of the multiplication in "optimized to 0". That is repeated for all the bit of the signal...

 

[sunjianhuigou]

HI:
Post simulation (choose it at the ISE's menu option) is simulation after the physical mapping process, it will consider the realistic delay of the cell and net, but the fuction simulation is a ideal case.

Had you used ythe input port in your design(always/assign)? if u justly declare the input port, or the width of the port is wrong? will induce this problem.

The result of the multiplication in "optimized to 0" :
[1] Firstly, if passed the Function Simulation(it make sure that your coding is ok)(!), but the Post Simulation had not passed, it should be the timing problem.
[2] Secondly, if u had solved the unconnected input port problem(!), u should to make sure that your input signals adding to the DUT(your design) at the board level is right.

 

[TrickyDicky]

Latches are generated because you put loads of logic into asynchronous processes and in those processes you did not assign every signal a value for every combination of inputs. When you do this, some signals have to hold their values for some combination of inputs so a memory is needed, hence a latch. The quickest fix is to make sure ever if has an "else" case and every case statement has a "when others => " case. Otherwise synchronise your design for an easier life.

The removal of logic is often because you connected some input to '0', or some other logic got stuck at 0. If you have logic that does not affect any output, that will also get stripped out.

I suggest you post some code here, as it looks like you have bad code all over.

 

[Sniesk]

Thanks to your advices i was able to go past the problem of the latches and the removed signals. I had a register with the reset port not connected so it was always in reset state.

I also did the post map simulation and all went fine, but still i am not able to make it work on the board. The input and the output (switches and led/display) are working, but it seems like it is not really calculating anything.

Now i don't really know what to do, as i even got no warning...
I'll post here my project, i know it is a mess, but it is my first try with vhdl. I hope some of you can help.

View attachment BOOTH.rar