Biasing problem of folded cascade amplifier reduce settling time

[r.mirtaji]

Hello dear friends,
I designed an amplifier as shown below
In order to bias the circuit, I initially used two voltage sources for Vb1 and Vb4
When I ran Simulink with this ideal voltage source settling time=20ns and selw rate=50V/us
When I changed the ideal voltage with the bias circuit The response of the circuit worsened
time=50ns and selw rate=30V/us
The reason for this problem is Vb1
The problem was solved because I only replaced Vb1 to the bias circuit with an ideal voltage source
The effect of bias circuit on circuit performance is less mentioned in books
How can this problem be solved?

 

[dick_freebird]

Some nodes want reduced impedance, starving
current will extend risetimes / slow slew rates.
But some nodes are specifically desired to be hi-Z
(whole point of cascoding) and starving the main
gain node inescapably makes the amplifier slow.
Lowering Znode will kill gain.

You could lower VB1 impedance by (for example)
making the bias rack use a feedback buffer with a
low source impedance, that makes a reference
device on the same bias rail null the master bias
current.

But you want to know that VB1 perturbation and
recovery is actually the problem.

Devices with large Cgd sitting on a bias rail are great
for perturbing the bias under hard slewing or HF
operation. Scaling or buffering those could be of
benefit (subject to other things like output current
specs, or stability issues from added phase-lag).

 

[frankrose]

20ns settling time is quite small. I guess it is only pre-layout simulation result and you haven't add C parasitic since you are playing with ideal biasing sources yet.... I would increase bias current and amplifier current too, to reach more spare in the system if you really need this speed, and rather start to estimate C parasitic from layout, add them to the the circuit and see what is happening. Not real or ideal bias should effect transient behavior mostly.

If still the bias is the bottleneck you can try to increase gm of the Vb1.4 diode connected FETs, and/or add a large capacitor in parallel.

 

[r.mirtaji]

Some nodes want reduced impedance, starving
current will extend risetimes / slow slew rates.
But some nodes are specifically desired to be hi-Z
(whole point of cascoding) and starving the main
gain node inescapably makes the amplifier slow.
Lowering Znode will kill gain.

You could lower VB1 impedance by (for example)
making the bias rack use a feedback buffer with a
low source impedance, that makes a reference
device on the same bias rail null the master bias
current.

But you want to know that VB1 perturbation and
recovery is actually the problem.

Devices with large Cgd sitting on a bias rail are great
for perturbing the bias under hard slewing or HF
operation. Scaling or buffering those could be of
benefit (subject to other things like output current
specs, or stability issues from added phase-lag).

--- Updated Nov 13, 2021 ---

Thank you for your time. dick_freebird and frankrose

Suppose we want to bias the F-1 circuit. The result of simulation as a buffer in the time domain is also obtained F-1
M24-25=60/1 M22-23=80/1 I22 to 25=70u
-----------------------------------------------------------------------
Now we want to replace an ideal source voltage with bias circuit(F-2).
As you can see settling time decreased from 18ns to 26ns
I42=70u! M32=70/4 gm=417U Rout32=644K CDS32=5.54E15 CGS32=2.26E-12
----------------------------------------------------------------------------
As we know, bias current cannot be high due to power consumption So we put the current
I42=10u M32=10/4 gm=59.66u Rout=150k CDS32= 793.7E-18 CGS32= -324.4E-15
As we can see, the phase and settling time is getting worse in F-3
------------------------------------------------------------------------------------
Is there a solution to approach the ideal state with the least power consumption
What is reason for the reduction of the system phase and the worsening of the settling time

 

[frankrose]

I think it makes no sense to focus too much on the biasing. Add large parallel C to the diode connected device if consumption is fixed and really it is an issue, I said it before already.
BTW in "real case" the |Vds|-|Vdsat| of M25,26 is ~10mV lower and the devices are on the edge of saturation. Not too lucky and can result in worse phase margin.

Have you tried to simulate in SS process corner?
Have you tried to change temperature?
Have you tried to add routing R,C,CC estimated parasitic?

These will have more influence on settling...

 

[r.mirtaji]

I think it makes no sense to focus too much on the biasing. Add large parallel C to the diode connected device if consumption is fixed and really it is an issue, I said it before already.
BTW in "real case" the |Vds|-|Vdsat| of M25,26 is ~10mV lower and the devices are on the edge of saturation. Not too lucky and can result in worse phase margin.

Have you tried to simulate in SS process corner?
Have you tried to change temperature?
Have you tried to add routing R,C,CC estimated parasitic?

These will have more influence on settling...

That you said is absolutely true " large parallel C to the diode connected device if consumption is fixed and really it is an issue"
Because i have to add a relatively large capacitor(1pf to 2 pf) and I did not consider this method to be used for compensation anywhere.
And I saw in the book and paper that I should M25,26 bias on the edge of saturation but i dont understand why
i didnt tried to simulate in SS process corner
You suggest I do this

 

[frankrose]

i didnt tried to simulate in SS process corner

Well, prepare for much higher speed degradation with slow-slow process. And check your design at least with the highest possible temperature too.

Cascoded devices normally operates close to the border of saturation/linear region, cause it ensures the highest output voltage swing and supply voltage range, and actually "low voltage cascoding" force low |Vds| for shielded devices, that is fine, but because of different variations (like temperature, process, supply or mismatch) it is highly recommended to add some spare, 50mV...150mV in typical/nominal corner to the |Vds|.

 

[r.mirtaji]

Well, prepare for much higher speed degradation with slow-slow process. And check your design at least with the highest possible temperature too.

Cascoded devices normally operates close to the border of saturation/linear region, cause it ensures the highest output voltage swing and supply voltage range, and actually "low voltage cascoding" force low |Vds| for shielded devices, that is fine, but because of different variations (like temperature, process, supply or mismatch) it is highly recommended to add some spare, 50mV...150mV in typical/nominal corner to the |Vds|.

Thank you I really appreciate your help.
I will definitely do this analysis and adjust the overhead voltage if necessary
I had another question
The frequency of the circuit that I am working on it is between 10Mhz and 20Mhz.
The library model I have is 130 nm with different types of MOS transistors like
(
1-nmos1v,nmos2v,nmos3v => Standard Vt ,
2-nmos1vhvt => High Vt,..,..,
3-nmos1vlvt => Low Vt,..,..,
4-nmos1vn => Native devices are without LOD effect and noise models
51-rfnmos1v,rfnmos2v,rfnmos3v,rfnmos1v_nw
)
Item number one, which is the standard model of the transistor, is used for what. Is it suitable for a circuit with my operating frequency?
The 1v,2v,3v indicates the breakdown voltage drain gate If so, why does it not give an error message when I set the bias higher than this value?
What does Native transistor do?
Are transistors RF used for a 10Mhz -frequency digital-to-analog converter?

 

[frankrose]

1, 20MHz is not so big if you have a 130nm technology. Normally you can build circuits up to 2GHz with such small transistors. So don't worry about standard Vt devices, they should be fine. Any other Vt devices require extra costs (extra mask layers) usually, try to avoid them.

2, actually simulator output log should contain warning messages, if you exceed a breakdown voltage. But it is easy to miss those. You can try to use "Device Check" in Virtuoso to see if there is a rule (max voltage, max current) violation under any analysis, at any time, how much is the overvoltage, how long does it takes, etc. That is pretty useful tool, browse for it, I don't remember how to use it.

3, Native transistor is usually an NMOS, which is fabricated in the undoped silicon substrate region (so not above a P dopant region), thus its Vth is basically 0V, but can vary from negative to positive values with process. It is very useful device for high-swing cascoding or to protect low voltage circuits, but it needs extra area, extra mask layers (=extra cost) and you cannot turn it off. Sometimes useful.

4, "10 MHz is pulsing DC." a former boss said, the point is that it is quite low frequency, and RF transistors are used on much higher freq, in the GHz ranges.