Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Behavioral simulation??????

Status
Not open for further replies.

lmtg

Member level 3
Joined
Jan 25, 2009
Messages
65
Helped
4
Reputation
8
Reaction score
2
Trophy points
1,288
Activity points
1,686
behavioral simulation

Is it normal that in behavioral simulation, with first clock the output is not correct and then with the second clock it is? How big of a deal is it for burning on fpga?
 

very very good question. an fpga expert told me that xilinx fpga takes around 70ps to run as expected. So if the first valid output is not during first clock cycle, it is absolutely OK. I think the first output is all zeros because fpga is initialized in this state.

Hope it helps.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top