behavior vs gate level code

[kuntul]

I am implementing a single cycle datapath in verilog and it has an ALU inside of it. One of the ALU functionality is to add.. and I did use the verilog '+' sign for this. If I had another module to perform add using gate level, will this make my clock speed much faster when I synthesize?

The report that I got when synthesizing is around 25Mhz and I want it to be around 40 MHz

 

[srizbf]

a 'gate level' hdl means , you know what the circuit is.

if that level is meeting your requiremnt you can get the reqd parameters.

'behaviour' - is designers 'top level'
it makes 'synthesizing' to produce what it thinks is best .

using 'gate level ' , you are fixing hdl simulators' freedom for choice.
srizbf
1stmay2010

 

[kuntul]

if I choose one over the other then does it affect on the speedup I will gain on the synthesis report?

 

[srizbf]

yes.

use 'gate level ' ,if you have the circuit that will
meet your specification.

srizbf
2ndmay2010

 

[kuntul]

so if I use Result1 + Result2 in verilog and on synthesis xilinx won't translate that to a carry lookahead gate adder? or any faster gate level addition?

 

[srizbf]

hello ,

now xilinx comes in. verilog code is generic .
using xilinx synthesis tool and mapping , it does it for the
particular xilinx family selected.

so what is going to be the final ,is on the mapping to the fpga family selected and resources available in it.

it will be different for different series .
(4000 , spartan etc...)

srizbf
2ndapril2010

 

[kuntul]

so when synthesizing the speedup I get from using gate level and say verilog code, result 1 + result 2 is the same as xilinx will optimize it for us?

 

[srizbf]

syntesised from gate level alone means it is only one netlist for given fpga .

could not get what is 'result1 ' and result2'

srizbf
3rdmay2010